4c15ed753e
I've lately discovered that misaligned PI DMA is also affected by RDRAM writes that must cross RDRAM row boundaries (2048 bytes). It is obvious in retrospect that the DMA implementation cannot generate a write burst across different rows, so its internal buffering must be segmented on RDRAM row boundaries. The PI DMA testsuite has been updated to cover this edge case as well: https://github.com/rasky/n64_pi_dma_test Ares now passes the updated testsuite in full (timing aside, which is close but not perfect). |
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| .. | ||
| bus.hpp | ||
| debugger.cpp | ||
| dma.cpp | ||
| io.cpp | ||
| pi.cpp | ||
| pi.hpp | ||
| serialization.cpp | ||