249 行
9.5 KiB
C++
249 行
9.5 KiB
C++
auto DMA::readByte(u32 address) -> u32 {
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n32 data;
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if((address & ~3) == 0x1f80'10f0) return data = readWord(address & ~3) >> 8 * (address & 3);
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if((address & ~3) == 0x1f80'10f4) return data = readWord(address & ~3) >> 8 * (address & 3);
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if((address & ~3) == 0x1f80'10f8) return data = readWord(address & ~3) >> 8 * (address & 3);
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if((address & ~3) == 0x1f80'10fc) return data = readWord(address & ~3) >> 8 * (address & 3);
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auto& channel = channels[address >> 4 & 7];
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if((address & 0x1fff'ff8c) == 0x1f80'1080) data = readWord(address & ~3) >> 8 * (address & 3);
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if((address & 0x1fff'ff8f) == 0x1f80'1084) data = channel.length.byte(0);
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if((address & 0x1fff'ff8f) == 0x1f80'1085) data = channel.length.byte(1);
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if((address & 0x1fff'ff8f) == 0x1f80'1086) data = channel.blocks.byte(0);
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if((address & 0x1fff'ff8f) == 0x1f80'1087) data = channel.blocks.byte(1);
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if((address & 0x1fff'ff8c) == 0x1f80'1088) data = readWord(address & ~3) >> 8 * (address & 3);
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if((address & 0x1fff'ff8c) == 0x1f80'108c) data = readWord(address & ~3) >> 8 * (address & 3);
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return data;
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}
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auto DMA::readHalf(u32 address) -> u32 {
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n32 data;
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if((address & ~3) == 0x1f80'10f0) return data = readWord(address & ~3) >> 8 * (address & 3);
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if((address & ~3) == 0x1f80'10f4) return data = readWord(address & ~3) >> 8 * (address & 3);
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if((address & ~3) == 0x1f80'10f8) return data = readWord(address & ~3) >> 8 * (address & 3);
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if((address & ~3) == 0x1f80'10fc) return data = readWord(address & ~3) >> 8 * (address & 3);
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auto& channel = channels[address >> 4 & 7];
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if((address & 0x1fff'ff8c) == 0x1f80'1080) data = readWord(address & ~3) >> 8 * (address & 3);
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if((address & 0x1fff'ff8e) == 0x1f80'1084) data = channel.length;
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if((address & 0x1fff'ff8e) == 0x1f80'1086) data = channel.blocks;
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if((address & 0x1fff'ff8c) == 0x1f80'1088) data = readWord(address & ~3) >> 8 * (address & 3);
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if((address & 0x1fff'ff8c) == 0x1f80'108c) data = readWord(address & ~3) >> 8 * (address & 3);
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return data;
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}
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auto DMA::readWord(u32 address) -> u32 {
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n32 data;
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//DPCR: DMA Control
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if(address == 0x1f80'10f0) {
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data.bit( 0, 2) = channels[0].priority;
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data.bit( 3) = channels[0].masterEnable;
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data.bit( 4, 6) = channels[1].priority;
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data.bit( 7) = channels[1].masterEnable;
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data.bit( 8,10) = channels[2].priority;
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data.bit(11) = channels[2].masterEnable;
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data.bit(12,14) = channels[3].priority;
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data.bit(15) = channels[3].masterEnable;
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data.bit(16,18) = channels[4].priority;
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data.bit(19) = channels[4].masterEnable;
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data.bit(20,22) = channels[5].priority;
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data.bit(23) = channels[5].masterEnable;
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data.bit(24,26) = channels[6].priority;
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data.bit(27) = channels[6].masterEnable;
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return data;
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}
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//DICR: DMA Interrupt
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if(address == 0x1f80'10f4) {
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data.bit( 0, 5) = irq.unknown;
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data.bit(16) = channels[0].irq.enable;
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data.bit(17) = channels[1].irq.enable;
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data.bit(18) = channels[2].irq.enable;
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data.bit(19) = channels[3].irq.enable;
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data.bit(20) = channels[4].irq.enable;
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data.bit(21) = channels[5].irq.enable;
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data.bit(22) = channels[6].irq.enable;
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data.bit(23) = irq.enable;
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data.bit(24) = channels[0].irq.flag;
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data.bit(25) = channels[1].irq.flag;
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data.bit(26) = channels[2].irq.flag;
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data.bit(27) = channels[3].irq.flag;
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data.bit(28) = channels[4].irq.flag;
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data.bit(29) = channels[5].irq.flag;
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data.bit(30) = channels[6].irq.flag;
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data.bit(31) = irq.flag;
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return data;
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}
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//unknown
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if(address == 0x1f80'10f8) {
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data = 0x7fe3'58d1;
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return data;
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}
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//unknown
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if(address == 0x1f80'10fc) {
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data = 0x00ff'fff7;
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return data;
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}
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auto& channel = channels[address >> 4 & 7];
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//DnMADR: DMA Base Address
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if((address & 0x1fff'ff8f) == 0x1f80'1080) {
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data.bit(0,23) = channel.address;
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}
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//DnBCR: DMA Block Control
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if((address & 0x1fff'ff8f) == 0x1f80'1084) {
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data.bit( 0,15) = channel.length;
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data.bit(16,31) = channel.blocks;
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}
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//DnCHCR: DMA Channel Control
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if((address & 0x1fff'ff8f) == 0x1f80'1088
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|| (address & 0x1fff'ff8f) == 0x1f80'108c
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) {
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data.bit( 0) = channel.direction;
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data.bit( 1) = channel.decrement;
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data.bit( 2) = channel.chopping.enable;
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data.bit( 9,10) = channel.synchronization;
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data.bit(16,18) = channel.chopping.dmaWindow;
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data.bit(20,22) = channel.chopping.cpuWindow;
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data.bit(24) = channel.enable;
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data.bit(28) = channel.trigger;
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data.bit(29,30) = channel.unknown;
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}
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return data;
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}
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auto DMA::writeByte(u32 address, u32 value) -> void {
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n32 data = value;
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if((address & ~3) == 0x1f80'10f0) return writeWord(address & ~3, data << 8 * (address & 3));
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if((address & ~3) == 0x1f80'10f4) return writeWord(address & ~3, data << 8 * (address & 3));
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if((address & ~3) == 0x1f80'10f8) return writeWord(address & ~3, data << 8 * (address & 3));
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if((address & ~3) == 0x1f80'10fc) return writeWord(address & ~3, data << 8 * (address & 3));
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auto& channel = channels[address >> 4 & 7];
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if((address & 0x1fff'ff8c) == 0x1f80'1080) writeWord(address & ~3, data << 8 * (address & 3));
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if((address & 0x1fff'ff8f) == 0x1f80'1084) channel.length.byte(0) = data;
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if((address & 0x1fff'ff8f) == 0x1f80'1085) channel.length.byte(1) = data;
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if((address & 0x1fff'ff8f) == 0x1f80'1086) channel.blocks.byte(0) = data;
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if((address & 0x1fff'ff8f) == 0x1f80'1087) channel.blocks.byte(1) = data;
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if((address & 0x1fff'ff8c) == 0x1f80'1088) writeWord(address & ~3, data << 8 * (address & 3));
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if((address & 0x1fff'ff8c) == 0x1f80'108c) writeWord(address & ~3, data << 8 * (address & 3));
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}
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auto DMA::writeHalf(u32 address, u32 value) -> void {
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n32 data = value;
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if((address & ~3) == 0x1f80'10f0) return writeWord(address & ~3, data << 8 * (address & 3));
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if((address & ~3) == 0x1f80'10f4) return writeWord(address & ~3, data << 8 * (address & 3));
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if((address & ~3) == 0x1f80'10f8) return writeWord(address & ~3, data << 8 * (address & 3));
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if((address & ~3) == 0x1f80'10fc) return writeWord(address & ~3, data << 8 * (address & 3));
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auto& channel = channels[address >> 4 & 7];
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if((address & 0x1fff'ff8c) == 0x1f80'1080) writeWord(address & ~3, data << 8 * (address & 3));
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if((address & 0x1fff'fffe) == 0x1f80'1084) channel.length = data;
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if((address & 0x1fff'fffe) == 0x1f80'1086) channel.blocks = data;
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if((address & 0x1fff'ff8c) == 0x1f80'1088) writeWord(address & ~3, data << 8 * (address & 3));
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if((address & 0x1fff'ff8c) == 0x1f80'108c) writeWord(address & ~3, data << 8 * (address & 3));
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}
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auto DMA::writeWord(u32 address, u32 value) -> void {
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n32 data = value;
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//DPCR: DMA Control
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if(address == 0x1f80'10f0) {
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channels[0].priority = data.bit( 0, 2);
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channels[0].masterEnable = data.bit( 3);
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channels[1].priority = data.bit( 4, 6);
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channels[1].masterEnable = data.bit( 7);
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channels[2].priority = data.bit( 8,10);
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channels[2].masterEnable = data.bit(11);
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channels[3].priority = data.bit(12,14);
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channels[3].masterEnable = data.bit(15);
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channels[4].priority = data.bit(16,18);
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channels[4].masterEnable = data.bit(19);
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channels[5].priority = data.bit(20,22);
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channels[5].masterEnable = data.bit(23);
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channels[6].priority = data.bit(24,26);
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channels[6].masterEnable = data.bit(27);
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sortChannelsByPriority();
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return;
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}
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//DICR: DMA Interrupt
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if(address == 0x1f80'10f4) {
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irq.unknown = data.bit( 0,5);
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irq.force = data.bit(15);
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channels[0].irq.enable = data.bit(16);
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channels[1].irq.enable = data.bit(17);
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channels[2].irq.enable = data.bit(18);
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channels[3].irq.enable = data.bit(19);
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channels[4].irq.enable = data.bit(20);
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channels[5].irq.enable = data.bit(21);
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channels[6].irq.enable = data.bit(22);
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irq.enable = data.bit(23);
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if(data.bit(24)) channels[0].irq.flag = 0;
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if(data.bit(25)) channels[1].irq.flag = 0;
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if(data.bit(26)) channels[2].irq.flag = 0;
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if(data.bit(27)) channels[3].irq.flag = 0;
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if(data.bit(28)) channels[4].irq.flag = 0;
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if(data.bit(29)) channels[5].irq.flag = 0;
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if(data.bit(30)) channels[6].irq.flag = 0;
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irq.poll();
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return;
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}
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//unused
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if(address == 0x1f80'10f8) {
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return;
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}
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//unused
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if(address == 0x1f80'10fc) {
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return;
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}
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auto& channel = channels[address >> 4 & 7];
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//DnMADR: DMA Base Address
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if((address & 0x1fff'ff8f) == 0x1f80'1080) {
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channel.address = data.bit(0,23);
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}
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//DnBCR: DMA Block Control
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if((address & 0x1fff'ff8f) == 0x1f80'1084) {
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channel.length = data.bit( 0,15);
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channel.blocks = data.bit(16,31);
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}
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//DnCHCR: DMA Channel Control
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if((address & 0x1fff'ff8f) == 0x1f80'1088
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|| (address & 0x1fff'ff8f) == 0x1f80'108c
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) {
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channel.direction = data.bit( 0);
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channel.decrement = data.bit( 1);
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channel.chopping.enable = data.bit( 2);
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channel.synchronization = data.bit( 9,10);
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channel.chopping.dmaWindow = data.bit(16,18);
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channel.chopping.cpuWindow = data.bit(20,22);
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channel.enable = data.bit(24);
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channel.trigger = data.bit(28);
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channel.unknown = data.bit(29,30);
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if(channel.id == OTC) {
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//OTC DMA hard-codes certain fields:
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channel.direction = 0;
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channel.decrement = 1;
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channel.chopping.enable = 0;
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channel.synchronization = 0;
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channel.chopping.dmaWindow = 0;
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channel.chopping.cpuWindow = 0;
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channel.unknown.bit(0) = 0;
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}
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channel.state = Waiting;
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channel.chain.length = 0;
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channel.counter = 1;
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}
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}
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